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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
Table 14: MR1 Op-Code Bit Definitions (Continued)
Feature
BT = burst type
Type
Write-only
OP
OP3
Definition
0b: Sequential (default)
Notes
1b: Interleaved
WC = wrap control
Write-only
OP4
0b: Wrap (default)
1b: No wrap
n WR = number of t WR clock
Write-only
OP[7:5]
001b: n WR = 3 (default)
1
cycles
Note:
010b: n WR = 4
011b: n WR = 5
100b: n WR = 6
101b: n WR = 7
110b: n WR = 8
All others: Reserved
1. The programmed value in n WR register is the number of clock cycles that determines
when to start internal precharge operation for a WRITE burst with AP enabled. It is de-
termined by RU ( t WR/ t CK).
Table 15: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC)
Notes 1–5 apply to all parameters and conditions
Burst C ycle Number and Burst Address Sequence
BL
BT
C3
C2
C1
C0
WC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
4
Any
X
X
0b
0b
Wrap
0
1
2
3
X
X
1b
0b
2
3
0
1
Any
X
X
X
0b
No
y
y + y + y +
wrap
1
2
3
8
Seq
X
0b
0b
0b
Wrap
0
1
2
3
4
5
6
7
X
X
X
0b
1b
1b
1b
0b
1b
0b
0b
0b
2
4
6
3
5
7
4
6
0
5
7
1
6
0
2
7
1
3
0
2
4
1
3
5
Int
X
X
X
X
0b
0b
1b
1b
0b
1b
0b
1b
0b
0b
0b
0b
0
2
4
6
1
3
5
7
2
0
6
4
3
1
7
5
4
6
0
2
5
7
1
3
6
4
2
0
7
5
3
1
Any
X
X
X
0b
No
Illegal (not supported)
wrap
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
46
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2010 Micron Technology, Inc. All rights reserved.
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